The Peripheral Component Interconnect Express (PCIe) interface serves as the backbone of modern high-performance computing, connecting CPUs to GPUs, SSDs, and network interface cards. As data-intensive workloads such as artificial intelligence (AI), machine learning (ML), and cloud computing continue to grow, the demand for higher bandwidth has necessitated a new standard.
However, designing circuits for Revision 6.0 presents severe signal integrity challenges:
A x16 configuration provides up to 256 GB/s of total bandwidth (128 GB/s in each direction).
Challenges and Considerations
The move to 64 GT/s required a departure from the traditional NRZ (Non-Return to Zero) signaling used in previous generations.
Up to 256 Gigabytes per second (GB/s) for a standard x16 configuration.
Moving away from NRZ (Non-Return to Zero), PAM4 is the secret sauce behind the speed increase. PAM4 transmits 2 bits of data per cycle instead of 1, effectively doubling the bandwidth without doubling the signal frequency. pci express base specification revision 60 pdf
The bandwidth provided by PCIe 6.0 Base Specification is tailored for infrastructure-heavy deployments:
1b/1b encoding, which eliminates the overhead found in previous generations (like 128b/130b). 2. Core Architectural Innovations
To support PAM4 signaling and modern packet integrity demands, PCIe 6.0 abandons the variable-sized packet framing used in generations 1.0 through 5.0. Instead, it introduces a fixed-sized Flow Control Unit (Flit) architecture. What is a Flit? Challenges and Considerations The move to 64 GT/s
PAM4 has a lower "signal-to-noise ratio" (SNR). This is why the spec introduces heavy-duty Forward Error Correction (FEC).
Practical Implications
Power consumption is a massive challenge in modern hyperscale data centers. PCIe 6.0 introduces a new, highly granular power management state known as . PAM4 transmits 2 bits of data per cycle
The specification is designed to operate over standard PCB materials (like low-loss Megtron 6 or equivalent) with trace lengths comparable to PCIe 5.0 topologies.