Synopsys Icc User Guide Pdf Verified |link| -

# 1. Placement Execution place_opt # 2. Clock Tree Synthesis Execution synthesize_clock_trees clock_opt # 3. Routing Execution route_design route_opt Use code with caution. Report Generation and Checking

| Common Issue | Where to find the solution in the Verified PDF | | :--- | :--- | | | Chapter 4: Placement Constraints (Pin placement guidelines) | | CTS produces high skew | Chapter 8: Clock Tree Synthesis - Skew groups and buffer sizing | | Route fails with DRCs | Appendix C: Routing strategy flowcharts | | Timing doesn't match PrimeTime | Chapter 13: Extraction correlation and "save_qrc" methodology |

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Ensure your link_library contains the target logic cells ( * ) and matches your physical macro layout files.

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